ESXi 5.0 supports only LAHF and SAHF CPU instructions?
A.
True
B.
False
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Explanation in:
http://pubs.vmware.com/vsphere-50/index.jsp?topic=/com.vmware.vsphere.install.doc_50/GUID-DEB8086A-306B-4239-BF76-E354679202FC.html
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True – vSphere Installation and Setup document, Page 29, System requirements
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Early AMD64 and Intel 64 CPUs lacked LAHF and SAHF instructions. AMD introduced the instructions with their Athlon 64, Opteron and Turion 64 revision D processors in March 2005[33][34][35] while Intel introduced the instructions with the Pentium 4 G1 stepping in December 2005.
he instructions LAHF and SAHF deal with five of the status flags, which are used primarily by the arithmetic and logical instructions.
LAHF (Load AH from Flags) copies SF, ZF, AF, PF, and CF to AH bits 7, 6, 4, 2, and 0, respectively (see Figure 3-22). The contents of the remaining bits (5, 3, and 1) are undefined. The flags remain unaffected.
SAHF (Store AH into Flags) transfers bits 7, 6, 4, 2, and 0 from AH into SF, ZF, AF, PF, and CF, respectively (see Figure 3-22).
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