What describes the non-blocking architecture deployed in M-Series switches?

A.
Allows data movement across the bus through CMM and finally to MPC for delivery

B.
Allows fencing of memory partitions into bit-buckets for data delivery

C.
Allows frames to be sent to destination ports based on the receiving ports availability

D.
Allows memory segmentation across the s/bar platform permitting data redirection based on
ASIC availability